Transition Based Input Test Vector Partitioning for Low Power Switching Activity S.saravanan, Har

Present complexity of System on Chip (SOC) has brought new challenges in low power design and testing. This shows that huge test pattern and its corresponding switching activity are one of the major problems. Due to this large number of test patterns the data transition time is also increased. More switching is also proportional to more number of transitions. This paper considers the problem of switching activity in scan based test pattern. This proposed approach is based on reducing the huge switching activity by partitioning the test vectors into groups. The number of transition is identified in each partition group. The groups having zero transition have lesser switching activities, so they are not considered equally with transition group for testing. Thus the test run time and number of switching is minimized. This in turn reduces the power consumption for testing. The proposed technique tested on ISCAS89 shows the significant reduction in overall switching activity of the test pattern.